The present invention relates generally to reading data from a memory, and more particularly, to a method and apparatus for synchronous read data sampling.
In a typical synchronous memory system, a memory controller provides clock and other control signals (e.g., read enable) to a memory device. On receipt of a read qualifying control signal from the memory controller, the memory device outputs the read data after an access “latency” delay. As the operating speed of processors and microcontrollers has increased significantly in recent years, so have the operating speeds of peripheral devices such as synchronous memory devices. However, as frequency increases, propagation delay and PVT (process, voltage and temperature) variations play a more significant role in data transfer. Typically, in synchronous data processing systems, there is a phase difference, owing to propagation delays, between the clock and data signals transferred between components such as the aforementioned memory controller and memory device, which tends to increase with frequency. This can lead to incorrect data sampling during read operations.
One known solution to this problem uses a phase locked loop (PLL) circuit and a feedback loop where the clock edges seen by the memory device and memory controller are aligned. However, this solution fails in cases where the propagation delay is around one clock cycle or greater, and has the further disadvantage of requiring extra silicon area for the PLL. An alternative known solution uses feedback of clock and control signals to compensate for delays. However, this has the disadvantage of requiring extra pins for the feedback signals. Thus, it would be advantageous to provide a processing system for synchronous read sampling without the above-mentioned drawbacks.